1. Field of the Invention
The present invention relates generally to a field effect transistor provided with a PHS (plated heat sink) on a FET chip.
2. Description of the Related Art
Such type of a field effect transistor (FET) will be discussed using a high-power GaAs FET as an example.
FIG. 1 is a plan view of the conventional high-power GaAs FET provided with a PHS (plated heat sink) of a gold plated layer on the back surface of the conventional GaAs substrate, and FIG. 2 is a section taken along line II--II of FIG. 1. In the shown high-power GaAs FET, a FET chip is formed with four unit cells 3 (shown by surrounding with two dotted lines) arranged in parallel. The unit cell 3 has a gate electrode, a drain electrode and a source electrode. These electrodes are comb-shaped configuration with finger-shaped gate electrode Gf, finger-shaped drain electrode Df and finger-shaped source electrode Sf, on an active region 2 formed in the surface portion of the substrate by ion implantation. Adjacent cells are connected by connecting respective source electrodes Sc to each other.
Similar structure can be realized in a multi-chip device constructed by combining a plurality of chips, each corresponding to one unit cell. However, in such case, due to positioning error between respective chips or differences of configuration of bonding wires connecting the chips, and other reasons, there are many factors which may cause degradation of high frequency characteristics, such as signal phase offset between the chips. Furthermore, the cost of assembling such devices becomes high. Thus, multi-chip devices are not practical.
In order to reduce thermal resistance, it is required to form the GaAs substrate 1 in a thickness of 30 to 50 .mu.m, and, in order to maintain strength of the chip, a gold plated PHS is required in a thickness of 10 to 30 .mu.m.
Upon loading such FET chip in a package 200 as shown in FIG. 3, a heat higher than or equal to a melting point of solder 100 is applied. At this time, due to difference of thermal expansion coefficients of the GaAs substrate 1 of the FET chip and the PHS 5, the cooled and bonded FET chip curls due to stress of thermal expansion. Accordingly, in the FET, bonding failure can be caused frequently to lower assembling yield of the FET.
As a solution for this, Japanese Unexamined Patent Publication (Kokai) No. Showa 63-131555 proposes a structure illustrated in FIGS. 4 and 5. Namely, the PHS is separated into a plurality of PHS fractions 5(5-1, 5-2, 5-3, 5-4 . . . ) by a plurality of slits 7(7-1,7-2, 7-3 . . . ) formed at a given interval. With such structure, deformation due to difference of thermal expansion coefficient upon loading in the package can be restricted and thus assembling yield can be improved.
However, by simply separating the PHS into a plurality of PHS fractions 5-1, 5-2 . . . by the slits 7-1, 7-2, 7-3 . . . , waving curling may be caused when the FET chip is mounted on the package 200, as shown in FIG. 6. Namely, at the portion where the slit 7 is not present, the layer structure becomes a two layer structure of the GaAs substrate 1 and the PHS 5 which causes local curling due to difference of thermal expansion coefficients. On the other hand, assuming that the electrode layer on the surface is thin enough to be ignored, at the portion where the slit is formed, the layer structure becomes a single layer of the GaAs substrate 1, in which deformation due to difference of the thermal expansion coefficients as not result. Furthermore, this portion has low mechanical strength due to absence of the PHS. As a result, while curling of the entire chip may not result, the portion of the GaAs substrate where the slit is provided is deformed to curl in the opposite direction to deforming direction of the portion where the slit is not provided, at quite small curvature due to the force to mechanically depressing the chip or the surface tension force of the molten solder. In general, stress of a thin film upon deformation of the thin film is inversely proportional to the curvature and proportional to the film thickness. Therefore, locally, quite large stress is concentrated in the GaAs substrate. In real terms, assuming that the layer thickness of the GaAs substrate is 30 .mu.m and the thickness of the PHS is 15 .mu.m, and width of the slit is about one tenth of the slit pitch, approximately 500 MPa of stress would be caused.
When about 300 MPa of stress is caused in the GaAs substrate, due to elevation of temperature during operation of the FET, shifting dislocation motion may be caused. This dislocation causes lowering of output of the FET with multiplication due to ion collision during FET operation. Thus, reliability of FET is lowered.